The manufacturing process for semiconductor read/write arrays (Random Access Memories) of n bits by m words has typically used some form of redundancy as a yield enhancement mechanism. In most cases, the redundancy mechanism is invoked after final functional test of the array and results in the array chip being assigned a specific part number depending on which bit is bad.
In the case where, for example, a 256.times.[array is desired, the array would be fabricated as a 256.times.9 structure and offered as 9 different part numbers. The part numbers would consist of either all original 8 words used or as any 1 of 8 combinations where the redundant ninth word is substituted for 1 of the 8 original words. Since the assignment of the array chip I/O pads is dependent on the particular word that is bad, the part numers are not interchangeable, except in the case of an all good chip.
If an array of this type fails in the field, it is not possible to substitute a good word for a bad word without physically replacing the chip.
The following patents and publications are directed to redundancy techniques for memory arrays. It is to be appreciated that the following art is not submitted to be the only, the best, or the most pertinent art.